CS5530A datasheet(89/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

PC/AT Compatibility Logic

Revision 1.1

4.5

PC/AT Compatibility Logic

The CS5530A’s PC/AT compatibility logic provides support

for the standard PC architecture. This subsystem also pro-

vides legacy support for existing hardware and software.

Support functions for the GX1 processor provided by these

subsystems include:

• ISA Subtractive Decode

• ISA Bus Interface

— Delayed PCI Transactions

— Limited ISA and ISA Master Modes

• ROM Interface

• Megacells

— Direct Memory Access (DMA)

— Programmable Interval Timer

— Programmable Interrupt Controller

— PCI Compatible Interrupts

• I/O Ports 092h and 061h System Control

— I/O Port 092h System Control

— I/O Port 061h System Control

— SMI Generation for NMI

• Keyboard Interface Function

— Fast Keyboard Gate Address 20 and CPU Reset

• External Real-Time Clock Interface

The following subsections give a detailed description for

each of these functions.

4.5.1

ISA Subtractive Decode

The CS5530A provides an ISA bus controller. The

CS5530A is the default subtractive-decoding agent, and

forwards all unclaimed memory and I/O cycles to the ISA

interface. For reads and writes in the first 1 MB of memory

(i.e., A23:A20 set to 0), MEMR# or MEMW# respectively

will be asserted. However, the CS5530A can be configured

using F0 Index 04h[1:0] to ignore either I/O, memory, or all

unclaimed cycles (subtractive decode disabled, F0 Index

41h[2:1] = 1x). Table 4-36 shows these programming bits.

Table 4-36. Cycle Configuration Bits

Bit

Description

F0 Index 04h-05h

PCI Command Register (R/W)

Reset Value = 000Fh

Memory Space: Allow the CS5530A to respond to memory cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

I/O Space: Allow the CS5530A to respond to I/O cycles from the PCI bus. 0 = Disable; 1 = Enable (Default).

F0 Index 41h

PCI Function Control Register 2 (R/W)

Reset Value = 10h

2:1

Subtractive Decode: These bits determine the point at which the CS5530A accepts cycles that are not claimed by another

device. The CS5530A defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the

Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be

done with care, as all ISA and ROM cycles are decoded subtractively.

00 = Default sample (4th clock from FRAME# active)

01 = Slow sample (3rd clock from FRAME# active)

1x = No subtractive decode

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