CS5530A datasheet(85/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

Table 4-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear)

Bit

Description

F1BAR+Memory Offset 06h-07h Second Level Gen. Traps/Timers SMI Status Register (RC)

Reset Value = 0000h

15:6

Reserved (Read to Clear)

PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration cycle (listed below)?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

Trapped access to F0 PCI header registers other than Index 40h-43h; SMI generation enabling is at F0 Index 41h[0].

Trapped access to F1 PCI header registers; SMI generation enabling is at F0 Index 41h[3].

Trapped access to F2 PCI header registers; SMI generation enabling is at F0 Index 41h[6].

Trapped access to F3 PCI header registers; SMI generation enabling is at F0 Index 42h[0].

Trapped access to F4 PCI header registers; SMI generation enabling is at F0 Index 42h[1].

SMI Source is Trapped Access to User Defined Device 3 (Read to Clear): SMI was caused by a trapped I/O or memory

access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[6].

SMI Source is Trapped Access to User Defined Device 2 (Read to Clear): SMI was caused by a trapped I/O or memory

access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[5].

SMI Source is Trapped Access to User Defined Device 1 (Read to Clear): SMI was caused by a trapped I/O or memory

access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[4].

SMI Source is Expired General Purpose Timer 2 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[1].

SMI Source is Expired General Purpose Timer 1 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[0].

Note: Reading this register clears all the SMI status bits.

A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read without

clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

F0 Index F4h

Second Level Power Management Status Register 1 (RC)

Reset Value = 84h

7:5

Reserved

Game Port SMI Status (Read to Clear): SMI was caused by a R/W access to game port (I/O Port 200h and 201h)?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

Game Port Read SMI generation enabling is at F0 Index 83h[4].

Game Port Write SMI generation enabling is at F0 Index 53h[3].

GPIO7 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO7 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[3].

GPIO5 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO5 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[2].

GPIO4 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO4 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[1].

GPIO3 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO3 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[0].

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