AD5770R datasheet(40/59 Pages) AD

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AD5770R

Data Sheet

Rev. 0 | Page 40 of 59

Address: 0x0B, Reset: 0x82, Name: SPI_REVISION

SPI Standard Vers ion

[7:0] VERSION (R)

Table 21. Bit Descriptions for SPI_REVISION

Bits

Bit Name

Description

Reset

Access

[7:0]

Version

SPI standard version. Analog Devices SPI standard used.

0x82

Address: 0x0C, Reset: 0x56, Name: VENDOR_L

Manufacturer ID

[7:0] VID[7:0] (R)

Table 22. Bit Descriptions for VENDOR_L

Bits

Bit Name

Description

Reset

Access

[7:0]

VID[7:0]

Manufacturer ID. Analog Devices ID = 0x0456.

0x56

Address: 0x0D, Reset: 0x04, Name: VENDOR_H

Manufacturer ID

[7:0] VID[15:8] (R)

Table 23. Bit Descriptions for VENDOR_H

Bits

Bit Name

Description

Reset

Access

[7:0]

VID[15:8]

Manufacturer ID. Analog Devices ID = 0x0456.

0x4

Address: 0x0E, Reset: 0x00, Name: STREAM_MODE

Stream Length

[7:0] LENGTH (R/W)

Table 24. Bit Descriptions for STREAM_MODE

Bits

Bit Name

Description

Reset

Access

[7:0]

LENGTH

Stream length. These bits set the length of registers addresses to increment/decrement when streaming

multiple bytes of data before looping back to the first register address. When the contents of this register

are cleared, register addresses increment/decrement when in streaming mode until the end of the

address space before looping to the last/first address and continuing to increment/decrement.

0x0

R/W

Address: 0x10, Reset: 0x20, Name: INTERFACE_CONFIG_C

Strict Entity Acces s

[7:6] RESERVED

[4:0] RESERVED

[5] STRICT_REGISTER_ACCESS (R)

Table 25. Bit Descriptions for INTERFACE_CONFIG_C

Bits

Bit Name

Description

Reset

Access

[7:6]

Reserved

Reserved.

0x0

STRICT_REGISTER_ACCESS

Strict register access. When this bit is set, all multibyte registers must be written to in a

single SPI transaction. The address used must be the address of the most significant

byte when address ascension is off or the address of the least significant byte when

address accession is on.

0x1

[4:0]

Reserved

Reserved.

0x0

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