AD5770R datasheet(27/59 Pages) AD

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Data Sheet

AD5770R

Rev. 0 | Page 27 of 59

SPI Frame Synchronization

The CS pin is used to frame data during an SPI transaction. A

falling edge on CS initiates a SPI transaction. Deasserting CS

during a SPI transaction terminates part or all of the data transfer.

If CS is deasserted (returned high) before the instruction phase

is complete, the transaction aborts and the AD5770R returns to

the ready state. If CS is deasserted before the first data word is

written, the transaction aborts and the AD5770R returns to the

ready state. If CS is deasserted after one or more data words have

been written, those completed data words are written or read, but

any partial written data words are aborted.

Streaming Mode

The CS pin can be held low, and multiple data bytes can be

shifted during the data phase, which reduces the amount of

overhead associated with data transfer. This mode of operation

is known as streaming mode. When in streaming mode, the

incremented or decremented after each byte of data is processed.

The ADDR_ASCENSION_MSB bit and ADDR_ASCENSION_

LSB bit in the INTERFACE_CONFIG_A register selects the

address increment or decrement. The default operation is to

decrement addresses when streaming data. Figure 72 illustrates

a streaming mode SPI write transaction in which the six input

registers are accessed using only a single instruction byte. The

byte is processed. Figure 73 illustrates a streaming mode SPI

read transaction in which the six DAC registers are accessed

using a decrementing address.

Single Instruction Mode

When the single instruction bit is set in the INTERFACE_

CONFIG_B register, streaming mode is disabled, and the

AD5770R is placed in single instruction mode. In single instruction

mode, the internal SPI state machine resets after the data phase as if

CS was deasserted, and awaits the next instruction. Single

instruction mode forces each data phase to be preceded with a

new instruction phase even though the CS line has not been

deasserted by the SPI master. Single instruction mode allows the

user to access one or more registers in a single synchronization

frame without having to deassert the CS line after each data bye.

The default for this bit is cleared, resulting in streaming mode

being enabled.

Figure 74 illustrates an SPI transaction in single instruction mode

in which the following sequence of events occur:

1. Sets the output range of Channel 1.

2. Enables the output of Channel 1.

3. Writes to the Channel 1 DAC register.

4. Reads the status register.

Multibyte Registers

If writing to a multibyte register, CS must be held low for the

whole transaction for the write to be valid. The address used

must be the address of the most significant byte. The ADDR_

ASCENSION_MSB bit and the ADDR_ASCENSION_LSB bit in

the INTERFACE_CONFIG_A register must be cleared. This

applies when reading or writing to any multibyte register in

both single instruction mode and streaming mode. Figure 75

illustrates a multibyte register access. The AD5770R contains 14

multibyte registers, as follows:

•

Six input registers.

•

Six DAC registers.

•

One input page mask register.

•

One DAC page mask register.

SDI

INSTRUCTION PHASE

CH5_INPUT_MSB ADDRESS

CH5_INPUT_MSB

DATA PHASE

CH5_INPUT_LSB

CH0_INPUT_MSB

CH0_INPUT_LSB

Figure 72. Streaming Mode SPI Write Transaction with Decrementing Address

SDI

SDO

INSTRUCTION PHASE

CH5_DAC_LSB ADDRESS

DON’T CARE

DATA PHASE

DON’T CARE

CH5_DAC_MSB

CH5_DAC_LSB

CH0_DAC_MSB

Figure 73. Streaming Mode SPI Read Transaction with Decrementing Address

SDI

SDO

INSTRUCTION PHASE

OUTPUT_RANGE_CH1 CH1_MODE

CH_CONFIG CH1 OUTPUT EN

CH1_DAC_MSB

MSB BYTE

LSB BYTE

STATUS DON’T CARE

DATA PHASE

STATUS

Figure 74. SPI Transaction in Single Instruction Mode

AD5770R Datasheet(PDF) 27 Page - Analog Devices

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