AD5770R datasheet(28/59 Pages) AD

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AD5770R

Data Sheet

Rev. 0 | Page 28 of 59

SDI

W CH3_DAC_MSB ADDRESS

CH3_DAC_MSB

CH3_DAC_LSB

INSTRUCTION PHASE

DATA PHASE

Figure 75. Multibyte Register Write

RESET FUNCTION

The AD5770R has an asynchronous RESET pin. For normal

operation, RESET is tied high. Asserting the RESET pin to logic

low for at least 10 ns resets all registers to their default values.

The reset function takes 100 ns, maximum. Data must not be

written to the device during this time.

The AD5770R has a software reset function that performs the

same function as the RESET pin, with the exception of not

resetting the INTERFACE_CONFIG_A register. The reset

function is activated by setting the SW_RESET_MSB and

SW_RESET_LSB bits in the INTERFACE_CONFIG_A register.

The SW_RESET_MSB and SW_RESET_LSB bits clear

automatically during a software reset.

A reset function must not be performed when the TEMP_

WARNING bit in the status register is high. Ensure that the device

reads the correct trim values from the internal memory.

LOAD DAC

The AD5770R DAC consists of double buffered registers for the

DAC code. Data for one or many channels can be written to the

input register without changing the DAC outputs. A load DAC

command issued to the device transfers input register content into

the DAC register, updating the DAC output.

Hardware LDAC Pin

The AD5770R has an active low LDAC pin that can synchronize

updates to the outputs of the DACs. When LDAC is held high,

DAC codes can be written to the input registers of the DAC

without affecting the output. When LDAC is taken low, the

contents of the input register are transferred to the DAC register

of the corresponding channel, and the output updates. The

LDAC idle high behavior is shown in Figure 2.

When the LDAC pin is held low before the last rising edge of CS

prior to the beginning of a new SPI transaction and the input

registers contents are modified, the update to the DAC output

happens when the LSB of the DAC input register is written. The

LDAC idle low behavior is shown in Figure 2 and Figure 3.

The LDAC pin functionality can be masked for any or all

channels by configuring the corresponding HW_LDAC_

MASK_CHx bits high in the HW_LDAC register, which is

useful in cases where only a selection of channels are required to

update synchronously.

Software LDAC

It is possible to transfer data from any or all input registers to

the corresponding DAC registers with a write to the SW_LDAC

are required to update synchronously.

Setting the SW_LDAC register for any channel updates the selected

channels DAC register with the input register contents. The

contents of the SW_LDAC register clear to 0x00 after a software

LDAC operation.

INPUT PAGE MASK REGISTER

Following a write to the input page mask register, the code

loaded into this register is copied into the input register of any

channels selected in the CH_SELECT register.

DAC PAGE MASK REGISTER

Following a write to the DAC page mask register, the DAC code

loaded into this register is copied into the DAC register of any

channels selected in the CH_SELECT register.

OUTPUT STAGES

Each of the six AD5770R channels has a programmable current

output stage that sets the required output current.

Channel 0 Sink Current Generator

To sink current on Channel 0, the sink current generator must

be enabled by setting the CH0_SINK_EN bit in the CHANNEL_

CONFIG register to one. On power-up, the sink current generator

is enabled.

Output Shutdown

On power-up, the outputs of each channel are in shutdown mode.

When a DAC output is in shutdown mode, the output current is

set to 0 mA. However, the bias circuitry for each IDACx channel

remains powered up, and only the output is shut down. The

shutdown bits for each register are located in the CHANNEL_

CONFIG register. When changing between output modes on a

DAC channel, the output stage of the channel must be shut down

to prevent glitches on the output.

Channel 0

Channel 0 of the AD5770R sinks up to 60 mA and sources up to

300 mA of current. This channel has three different modes of

operation. The CH0_MODE bits in the OUTPUT_RANGE_CH0

for Channel 0 are listed in Table 8.

On power-up, Channel 0 defaults to the 0 mA to 300 mA range.

Channel 0 has a sinking only mode of −60 mA to 0 mA. In

this mode, the DAC has a zero-scale output of −60 mA and a

full-scale output of 0 mA. To enter this mode safely without

output glitches, the output must be shut down first by setting

CH0_SHUTDOWN_B high in the CHANNEL_CONFIG register.

Channel 0 has a sourcing and sinking mode where the DAC has

a zero-scale output of −60 mA and a full-scale output of +300 mA.

To reduce glitches on the output of Channel 0, CH0_MODE

must be configured before taking the output out of shutdown.

AD5770R Datasheet(PDF) 28 Page - Analog Devices

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