Data Sheet

AD5770R

Rev. 0 | Page 11 of 59

Pin No.

Mnemonic

Type

8F

1

Description

D5

CDAMP_IDAC4

AI

Damping Capacitor for IDAC4. Connect a 10 nF capacitor between this pin and the PVDD4

supply.

D7

CDAMP_IDAC3

AI

Damping Capacitor for IDAC3. Connect a 10 nF capacitor between this pin and the PVDD3

supply.

E1

IREF

AI/O

resistor, connect this pin directly to REFGND via a low drift, 2.5 kΩ external resistor.

E2

REFGND

S

Reference Supply Ground Pin. Connect this pin with a low impedance path to AGND. If using

connection to AGND.

E5

AVDD

S

Analog Power Supply. AVDD must be between 2.9 V and 5.5 V. This pin supplies power to the

analog circuit blocks on the device. This pin must be at the same potential as DVDD.

E7

A

DI

Active Low Control Input.

A

A

is used to frame data during a SPI transaction. When

A

A

is low,

data is transferred on the rising edges of SCLK.

F1

VREF_IO

AI/O

Voltage Reference Input/Output. When the internal reference is enabled, the buffered 1.25 V

reference voltage can be made available on this pin. When the internal reference is disabled, an

external reference must be applied to this pin. The external reference voltage must be 1.25 V or

2.5 V.

F2

A

DO

Active Low Output. When

A

A

goes low, this alerts the user of a change in the status

register. User must read the status register to deassert this pin.

F3, F4

DGND

S

Digital Power Supply Ground.

F5

DVDD

S

Digital Power Supply. DVDD must be between 2.9 V and 5.5 V. This pin supplies power to the

digital core and internal oscillator blocks on the device. This pin must be at the same potential

as AVDD.

F6

A

DI

Logic Input. Pulsing this pin low allows any or all DAC registers to be updated if the input

registers have new data, allowing any or all DAC outputs to update synchronously.

Alternatively, this pin can be tied low.

F7

SDI

DI

Serial Data Input. Data to be written to the device is provided on this input and is clocked into

the register on the rising edge of SCLK.

G1

CREF

AI/O

Filter Capacitor for Voltage Reference. A 0.1 µF capacitor connected from the CREF pin to AGND

is recommended to achieve the specified performance from the AD5770R.

G2

A

DI

Active Low Reset Input. Tie this pin high for normal operation. Asserting this pin low resets the

AD5770R to the default configuration.

G3

MUX_OUT

AI/O

Analog Output. An external analog-to-digital converter (ADC) reads voltages on this pin for

diagnostic purposes. Use external excitation current for the temperature sensing diode and

force the current on this pin.

G4

CREG

AI/O

Filter Capacitor for Internal Regulator. A 1 µF capacitor connected from the CREG pin to AGND

is recommended to achieve the specified performance from the AD5770R.

G5

SDO

DO

Serial Data Output. A read back operation provides data on this output pin as a serial data

stream. Data is clocked out on the falling edge of SCLK and is valid on the rising edge of SCLK.

G6

IOVDD

S

Logic Power Supply. IOVDD must be between 1.65 V and 5.5 V. This pin supplies power to the

serial interface circuit blocks on the device.

G7

SCLK

DI

Serial Clock Input. Data is clocked into the input shift register on the rising edge of the serial

clock input. Data can be transferred at rates up to 20 MHz when writing to the AD5770R. This

pin has a maximum speed of 10 MHz when performing a read operation from the AD5770R.

1

AO is analog output, S is power, AI is analog input, DNC is do not connect, AI/O is analog input and output, DI is digital input, and DO is digital output.