AD5770R datasheet(7/59 Pages) AD

7 / 59 page

Data Sheet

AD5770R

Rev. 0 | Page 7 of 59

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments2

Output Noise

900

nA rms

0.1 Hz to 10 Hz, Channel 0, 0 mA to 300 mA

range, DAC register loaded to full scale

180

nA rms

0.1 Hz to 10 Hz, Channel 1, 0 mA to 140 mA low

noise range, DAC register loaded to full scale

400

nA rms

0.1 Hz to 10 Hz, Channel 2, 0 mA to 150 mA

range, DAC register loaded to full scale

300

nA rms

0.1 Hz to 10 Hz, Channel 3, Channel 4, Channel 5,

0 mA to 100 mA range, DAC register loaded to

full scale

PVDDx AC PSRR

−98

100 Hz

−87

1 kHz

−67

10 kHz

−23

1000 kHz

−8

3000 kHz

See the Terminology section.

Temperature range is −40°C to +105°C, typically at 25°C.

TIMING SPECIFICATIONS

Table 3.

Parameter

1.65 V ≤ IOVDD ≤ 5.5 V

Unit

Test Conditions/Comments

ns min

SCLK cycle time, write operation.

100

ns min

SCLK cycle time, read operation.

ns min

SCLK high time.

ns min

SCLK low time.

ns min

CS to SCLK rising edge setup time.

ns min

Data setup time.

ns min

Data hold time.

ns min

SCLK rising edge to CS rising edge. LDAC idle high mode.

t71

250

ns min

SCLK rising edge to CS rising edge. LDAC idle low mode.

ns min

CS high time.

ns min

CS rising edge to SCLK rising edge.

t10

ns min

SCLK rising edge to CS falling edge.

t11

ns max

SDO data valid from SCLK falling edge.

t12

ns min

CS rising edge to SDO disabled.

t13

100

ns min

LDAC pulse width low.

t14

ns min

LDAC falling edge to CS rising edge.

t15

100

ns min

SCLK rising edge to LDAC falling edge.

t16

ns min

RESET minimum pulse width low.

t17

100

ns max

RESET pulse activation time.

t7 ≥ 250 ns only applies to the first SCLK rising edge to CS rising edge after LDAC (IDLEL LOW) falling edge. t7 ≥ 0 ns applies for all other SCLK rising edge to CS rising edge.

Refer to Figure 3.

Table 4. LDAC Idle Low Timing

Parameter

1.65 V ≤ IOVDD ≤ 5.5 V

Unit

Test Conditions/Comments

250

ns min

SCLK rising edge to CS rising edge. The first SCLK rising edge to CS rising edge after

LDAC idle low falling edge.

ns min

SCLK rising edge to CS rising edge.

ns min

LDAC falling edge to CS rising edge.

AD5770R Datasheet(PDF) 7 Page - Analog Devices

AD5770R Datasheet(HTML) 7 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL