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C161 Datasheet(PDF) 172 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 172 Page - Infineon Technologies AG |
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172 / 400 page  &3, 7KH([WHUQDO%XV ,QWHUIDFH User’s Manual 9-8 1999-08 External Data Bus Width The EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit data bus uses PORT0, while an 8-bit data bus only uses P0L, the lower byte of PORT0. This saves on address latches, bus transceivers, bus routing and memory cost on the expense of transfer time. The EBC can control word accesses on an 8-bit data bus as well as byte accesses on a 16-bit data bus. Word accesses on an 8-bit data bus are automatically split into two subsequent byte accesses, where the low byte is accessed first, then the high byte. The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer. Byte accesses on a 16-bit data bus require that the upper and lower half of the memory can be accessed individually. In this case the upper byte is selected with the BHE signal, while the lower byte is selected with the A0 signal. So the two bytes of the memory can be enabled independent from each other, or together when accessing words. When writing bytes to an external 16-bit device, which has a single CS input, but two WR enable inputs (for the two bytes), the EBC can directly generate these two write control signals. This saves the external combination of the WR signal with A0 or BHE. In this case pin WR serves as WRL (write low byte) and pin BHE serves as WRH (write high byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The respective byte will be written on both data bus halfs. When reading bytes from an external 16-bit device, whole words may be read and the C161PI automatically selects the byte to be input and discards the other. However, care must be taken when reading devices that change state when being read, like FIFOs, interrupt status registers, etc. In this case individual bytes should be selected using BHE and A0. Note: PORT1 becomes available for general purpose IO, when none of the BUSCON registers selects a demultiplexed bus mode. Table 9-2 Bus Mode Versus Performance Bus Mode Transfer Rate (Speed factor for byte/word/dword access) System Requirements Free IO Lines 8-bit Multiplexed Very low ( 1.5 / 3 / 6 ) Low (8-bit latch, byte bus) P1H, P1L 8-bit Demultipl. Low ( 1 / 2 / 4 ) Very low (no latch, byte bus) P0H 16-bit Multiplexed High ( 1.5 / 1.5 / 3 ) High (16-bit latch, word bus) P1H, P1L 16-bit Demultipl. Very high ( 1 / 1 / 2 ) Low (no latch, word bus) --- |
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