AX58100 datasheet(14/71 Pages) ASIX

14 / 71 page

AX58100

EtherCAT Slave Controller

1.4.7

SPI Master

Pin Name

Type

Pin No

Pin Description

MSS[3:0]

69, 67,

53, 60

SPI Master Slave Select

MSCLK

SPI Master SCLK

MMOSI

SPI Master MOSI

MMISO

SPI Master MISO

MINT

SPI Master Interrupt in

MTRG

SPI Master Trigger in

MDRLD

SPI Master ADC Data Ready / DAC Data Loaded

Table 1-9: SPI Master Pin Description

1.4.8

Port 2 MII

Pin Name

Type

Pin No

Pin Description

MCLK

MII Clock

25 MHz clock source for Ethernet PHYs

LINK

Provided by the PHY if a 100 Mbps (Full Duplex) link is established

MDC

PHY Management Interface clock

MDIO

PHY Management Interface data

TXD[3]

Transmit data [3]

TXD[2:1] \

TX_SH[1:0]

66, 42

Transmit data [2:1]

This pin is input direction during chip reset stage used to bootstrap the mode

setting to decide the external PHY’s TXD phase shift, please refer to Section 3.1

TXD[0] \

LINK_POL

Transmit data [0]

These pins are input direction during chip reset use to bootstrap the mode setting

to decide external PHY’s LINK polarity, please refer to Section 3.1

TX_EN

Transmit enable

RX_CLK

Receive Clock

RXD[3:0]

8, 76, 75,

Receive data

RX_ER

Receive error

RX_DV

Receive data valid

Table 1-10: Port 2 MII Pin Description

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