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AX58100 Datasheet(PDF) 6 Page - ASIX Electronics Corporation

Part # AX58100
Description  EtherCAT Slave Controller
PDF  71 Pages
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Manufacturer  ASIX [ASIX Electronics Corporation]
Direct Link  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX58100 Datasheet(HTML) 6 Page - ASIX Electronics Corporation

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AX58100
EtherCAT Slave Controller
Copyright © 2018-2019 ASIX Electronics Corporation. All rights reserved.
List of Figures
FIGURE 0-1: AX58100 TYPICAL APPLICATIONS DIAGRAM .................................................................................................2
FIGURE 1-1: AX58100 BLOCK DIAGRAM............................................................................................................................8
FIGURE 1-2: AX58100 PINOUT DIAGRAM...........................................................................................................................9
FIGURE 3-1: AX58100 I2C EEPROM LAYOUT .................................................................................................................20
FIGURE 4-1: POWER ON RESET (POR) TIMING DIAGRAM .................................................................................................39
FIGURE 4-2: POWER-UP SEQUENCE TIMING DIAGRAM......................................................................................................40
FIGURE 4-3: WRITE ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS) .....................................................................41
FIGURE 4-4: WRITE ACCESS (2 ADDRESS BYTES, 32 KBIT - 4 MBIT EEPROMS) ...............................................................41
FIGURE 4-5: READ ACCESS (1 ADDRESS BYTE, UP TO 16 KBIT EEPROMS) .......................................................................42
FIGURE 4-6: PORT 2 MII TX TIMING DIAGRAM ................................................................................................................43
FIGURE 4-7: PORT 2 MII RX TIMING DIAGRAM ................................................................................................................44
FIGURE 4-8: MDC/MDIO WRITE ACCESS.........................................................................................................................45
FIGURE 4-9: MDC/MDIO READ ACCESS ..........................................................................................................................45
FIGURE 4-10: LATCH TIMING ..........................................................................................................................................46
FIGURE 4-11: SYNC TIMING .............................................................................................................................................46
FIGURE 4-12: DIGITAL INPUT: INPUT DATA SAMPLED AT SOF, IO CAN BE READ IN THE SAME FRAME ..............................47
FIGURE 4-13: DIGITAL INPUT: INPUT DATA SAMPLED WITH LATCH_IN ..........................................................................47
FIGURE 4-14: DIGITAL OUTPUT TIMING ............................................................................................................................47
FIGURE 4-15: OE_EXT TIMING.........................................................................................................................................47
FIGURE 4-16: BASIC MOSI/MISO TIMING ........................................................................................................................49
FIGURE 4-17: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 1 BYTE READ DATA) WITH WAIT STATE BYTE...........50
FIGURE 4-18: PDI SPI SLAVE READ ACCESS (2 BYTE ADDRESSING, 2 BYTE READ DATA) WITH WAIT STATE BYTE...........51
FIGURE 4-19: PDI SPI SLAVE WRITE ACCESS (2 BYTE ADDRESSING, 1 BYTE WRITE DATA) ...............................................52
FIGURE 4-20: PDI SPI SLAVE WRITE ACCESS (3 BYTE ADDRESSING, 1 BYTE WRITE DATA) ...............................................53
FIGURE 4-21: FUNCTION SPI SLAVE WITH SHARE PIN TIMING DIAGRAM ..........................................................................54
FIGURE 4-22: FUNCTION SPI SLAVE WITH INDIVIDUAL PIN TIMING DIAGRAM .................................................................54
FIGURE 4-23: PDI LOCAL BUS READ ACCESS (WITHOUT PRECEDING WRITE ACCESS).......................................................55
FIGURE 4-24: PDI LOCAL BUS WRITE ACCESS (WRITE AFTER RISING EDGE NWR, WITHOUT PRECEDING WRITE ACCESS) 55
FIGURE 4-25: PDI LOCAL BUS SEQUENCE OF TWO WRITE ACCESSES AND A READ ACCESS ...............................................56
FIGURE 4-26: PDI LOCAL BUS WRITE ACCESS (WRITE AFTER FALLING EDGE LWRN)......................................................56
FIGURE 4-27: FUNCTION LOCAL BUS SIGNAL READ ACCESS............................................................................................59
FIGURE 4-28: FUNCTION LOCAL BUS WRITE ACCESS (LATE SAMPLE = 0) .......................................................................59
FIGURE 4-29: FUNCTION LOCAL BUS WRITE ACCESS (LATE SAMPLE = 1) .......................................................................59
FIGURE 4-30: PWMX TIMING ...........................................................................................................................................61
FIGURE 4-31: ONLY PWM CHANNEL 2 SHIFT DIAGRAM ..................................................................................................62
FIGURE 4-32: BBM (BREAK BEFORE MAKE) TIMING DIAGRAM.......................................................................................63
FIGURE 4-33: ONE SHOT WITH MULTI STEP TIMING DIAGRAM .........................................................................................63
FIGURE 4-34: ABZ TIMING DIAGRAM...............................................................................................................................64
FIGURE 4-35: CW/CCW TIMING DIAGRAM ......................................................................................................................64
FIGURE 4-36: CLK/DIR TIMING DIAGRAM.......................................................................................................................64
FIGURE 4-37: HALL TIMING DIAGRAM..............................................................................................................................64
FIGURE 4-38: SPI MASTER TIMING ...................................................................................................................................66
FIGURE 4-39: MMISO/MMOSI TIMING ...........................................................................................................................66
FIGURE 4-40: SPI MDRLD READY TIMEOUT TIMING ......................................................................................................67
FIGURE 4-41: SPI MTRG TRIGGER PULSE TIMEOUT ........................................................................................................67
FIGURE 4-42: SPI MDRLD TRIGGER LDAC GAP AND WIDTH TIMING ............................................................................67



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