AX58100 datasheet(58/71 Pages) ASIX

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AX58100

EtherCAT Slave Controller

TWR_delay < Twrite_int (Write after rising edge

-of WR)

TWR_delay

without preceding write access or

TWR_delay ≥ Twrite_int (Write after rising edge

of WR)

8-bit access, absolute worst case with

preceding write access (TWR_delay= min,

TWR_int=max, Write after rising edge of

WR)

180

16-bit access, absolute worst case with

preceding write access (TWR_delay=min,

TWR_int=max, Write after rising edge of

WR)

260

write_int

Internal write

time

8-bit access

180

16-bit access

260

WR_delay

Delay between WR deassertion and

assertion

Coll

Extra read delay RD access directly

follows WR access with

the same address (8-bit

accesses or 8-bit WR

and 16-bit RD)

different addresses or

16-bit accesses

TWR_to_RD

Delay between WR deassertion and RD

assertion

CS_WR_overlap

Time both CS and WR have to be

deasserted simultaneously (only if

CS is deasserted at all)

CS_RD_overlap

Time both CS and RD have to be

deasserted simultaneously (only if

CS is deasserted at all)

Table 4-14: PDI Local Bus Timing Table

AX58100 Datasheet(PDF) 58 Page - ASIX Electronics Corporation

AX58100 Datasheet(HTML) 58 Page - ASIX Electronics Corporation

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