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AX58100 Datasheet(PDF) 57 Page - ASIX Electronics Corporation |
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AX58100 Datasheet(HTML) 57 Page - ASIX Electronics Corporation |
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57 / 71 page  57 Copyright © 2018-2019 ASIX Electronics Corporation. All rights reserved. AX58100 EtherCAT Slave Controller Symbol Description Min Typ Max Units TCS_to_BUSY BUSY driven and valid after CS assertion - - 45 ns TADR_BHE_setup ADR and BHE valid before RD assertion 0 - - ns TRD_to_DATA_driven DATA bus driven after RD assertion 0 - - ns TRD_to_BUSY BUSY asserted after RD assertion 0 - 10 ns Tread External read time (RD assertion to BUSY deassertion) with normal read busy output (0x0152[0]). Additional 20 ns if delayed read busy output is configured. ns without preceding write access or TWR_to_RD ≥ Tprec_write + TColl or configuration: write after falling edge of WR - - Tread_int with preceding write access and TWR_to_RD < Tprec_write + TColl - - Tread_int + Tprec_write + TColl - TWR_to_RD 8-bit access, absolute worst case with preceding write access (TWR_to_RD=min, Tprec_write =max, TColl=max) - - 420 16-bit access, absolute worst case with preceding write access (TWR_to_RD=min, Tprec_write =max, TColl=max) - - 560 T read_int Internal read time 8-bit access - - 220 ns 16-bit access 300 T prec_write Time for preceding write access 8-bit access - - 180 ns 16-bit access 260 TBUSY_to_DATA_valid DATA bus valid after device BUSY is deasserted normal read busy output - - 5 ns delayed read busy output -15 T ADR_BHE_to_DATA_invalid DATA invalid after ADR or BHE change 0 - - ns T CS_RD_to_DATA_release DATA bus released after CS deassertion or RD deassertion 2.5 - 7.5 ns T CS_to_BUSY_release BUSY released after CS deassertion 2.5 - 8.5 ns T CS_delay Delay between CS deassertion an assertion 5 - - ns T RD_delay Delay between RD deassertion and assertion 5 - - ns T ADR_BHE_DATA_setup ADR, BHE and Write DATA valid before WR deassertion 6.5 - - ns T ADR_BHE_DATA_hold ADR, BHE and Write DATA valid after WR deassertion 2 - - ns T WR_active WR assertion time 8.5 - - ns T BUSY_to_WR_CS WR or CS deassertion after BUSY deassertion 0 - - ns T WR_to_BUSY BUSY assertion after WR deassertion - - 12 ns T write External write time (WR assertion to BUSY deassertion) ns Configuration: write after falling edge of WR (act. low) 0 - Twrite_int with preceding write access and - Twrite_int - |
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