AX58100 datasheet(15/71 Pages) ASIX

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AX58100

EtherCAT Slave Controller

2 Function Description

Clocks/Resets

The AX58100 requires a crystal (25MHz, ±25 PPM at room temperature) as the clock source, internal PLL

generates the 100MHz clock for EtherCAT Slave Controller (ESC) and others function used.

The AX58100 have three reset sources, during the VCCK power-on, the internal Power-On-Reset (POR) can

generate a reset pulse to reset all the function blocks when the VCCK power pin rise to a certain threshold voltage

level. Second reset is RSTn pin to do the fundamental reset. And third, EtherCAT command reset, the EtherCAT

master can sent reset sequence to force AX58100 reset. AX58100 also supports a reset output RSTO polarity

bootstrap configuration (RSTO_POL).

EtherCAT Slave Controller (ESC)

The AX58100 implements a 3-port EtherCAT slave controller (ESC), licensed from Beckhoff Automation, with 9

Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit

Distributed Clock.

Port 0 and 1 integrate embedded Ethernet PHYs, and port 2 is an optional MII interface which are multi-function

pins shared with others interfaces (i.e. PWM, Hall, Local Bus, Digital I/O). Packets are forwarded in the following

order: Port 0->EtherCAT Processing Unit->Port 1->Port 2.

The Process Data Interface (PDI, also name host interface) provides SPI slave, asynchronous 8/16-bit

microcontroller interface (also name Asynchronous Local Bus) and Digital I/O. The SPI slave and asynchronous

8/16-bit Local Bus interface will be used when external MCU in employed the slave system, and the Digital I/O is

used for when direct I/O control.

The AX58100 supports function register mirror from/to ESC memory space, the mirror registers located at process

data memory address from 0x3000 to 0x33FF.

For detailed information on the EtherCAT technology, the EtherCAT core mechanisms, and major features we

refer to the official standard documentations and guidelines available from ETG (www.ethercat.org, ETG.1000),

IEC (http://www.iec.ch, IEC61158, IEC61784-2, IEC 61800-7), and Beckhoff (http://www.beckhoff.de, technical

specification) web sites.

Ethernet PHY

The AX58100 embedded two DSP-based Ethernet PHYs, fully compliant with the 100BASE-TX and

100BASE-FX Ethernet standards such as IEEE 802.3u, and ANSI X3.263-1995 (FDDI-TP-PMD). In copper

mode supports the MDI/MDIX auto-crossover function (HP Auto-MDIX).

Bridge Function

The AX58100 has two memory spaces, one for ESC and one for AX58100 specified functions. The bridge handles

data synchronization between ESC’s memory and function registers, use EthterCAT packet’s SOF, EOF, ESC

control signal, SYNCx and LATx, PDI chip select (ESC and function) asserts and de-assert, the PWM cycle starts,

mirror could be enabled independent, the interrupt related registers mirror (INTCR and INTSR) are also enabled

when any function mirror is enabled.

AX58100 Datasheet(PDF) 15 Page - ASIX Electronics Corporation