AX58200 datasheet(147/180 Pages) ASIX

147 / 180 page

147

AX58200

EtherCAT Slave Controller SoC

3.11.3 I2S Dynamic Characteristics

Symbol

Parameter

Min

Max

Unit

Test Conditions

tw(CKH)

I2S clock high time

Master fPCLK = MHz, data: 24 bits, audio

frequency = 256 KHz

tw(CKL)

I2S clock low time

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

DuCy(SCK)

I2S slave input clock

duty cycle

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

tv(SD_ST)

Data output valid time

Slave transmitter (after enable edge)

th(SD_ST)

Data output hold time

Slave transmitter (after enable edge)

tv(SD_MT)

Data output valid time

Master transmitter (after enable edge)

th(SD_MT)

Data output hold time

Master transmitter (after enable edge)

tw(CKH)

tw(CKL)

th(WS)

tv(WS)

th(SD_ST)

LSB transmit

(2)

MSB transmit

Bitn transmit

LSB transmit

LSB receive

(2)

MSB receive

Bitn receive

LSB receive

tsu(SD_MR)

th(SD_MR)

SDtransmit

SDreceive

WS output

CPOL = 1

CPOL = 0

tv(SD_ST)

Figure 3.11-4 I2S Master Mode Timing Diagram

AX58200 Datasheet(PDF) 147 Page - ASIX Electronics Corporation

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