AX58200 datasheet(150/180 Pages) ASIX

150 / 180 page

150

AX58200

EtherCAT Slave Controller SoC

3.11.5 USCI - SPI Dynamic Characteristics

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)

tCLKH

Clock output High time [*1]

TSPICLK / 2

tCLKL

Clock output Low time [*1]

TSPICLK / 2

tDS

Data setup time

tDH

Data hold time

Data output valid time

SPI MASTER MODE (VDD = 1.8~2.0 V, 30 PF LOADING CAPACITOR)

tCLKH

Clock output High time [*1]

TSPICLK / 2

tCLKL

Clock output Low time [*1]

TSPICLK / 2

tDS

Data setup time

tDH

Data hold time

Data output valid time

Note:

The minimum clock period for SPICLK is 10.4 ns (96 MHz).

CLKP=0, TX_NEG=1, RX_NEG=0

CLKP=1, TX_NEG=0, RX_NEG=1

CLKP=0, TX_NEG=0, RX_NEG=1

CLKP=1, TX_NEG=1, RX_NEG=0

MISO

MOSI

Data Valid

SPICLK

MISO

MOSI

Data Valid

CLKP=0

CLKP=1

tDS

tDH

tDS

tDH

tCLKH

tCLKL

Figure 3.11-7 SPI Master Mode Timing Diagram

AX58200 Datasheet(PDF) 150 Page - ASIX Electronics Corporation

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