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CS98200 Datasheet(PDF) 14 Page - Cirrus Logic

Part # CS98200
Description  New Highly-Integrated Processor for Tommorrow DVD Players and DVD Receivers
PDF  60 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS98200 Datasheet(HTML) 14 Page - Cirrus Logic

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Copyright 2002 Cirrus Logic (All Rights Reserved)
DS581PP2
CS98200
Next Generation DVD Processor
Figure 6. DVD Loader CD Interface Formats
15
0
1
CD_ B C K
CD_ LRCK
DA T A
C2 P 0
14 13 12 11 10 9
8
7
6
5
4
3
2
Invalid
0
15
0
1
14 13 12 11 10 9
8
7
6
5
4
3
2
In va lid
M S BLSB
MSBLS B
Lo wer (L eft Channel)
Upper (Left Channe l)
Lower (Right Channel)
Uppe r (Righ t Channel)
32-bit B C K , MS B First, R ig ht C han nel L ow , C 2P 0 LS B F irst, D a ta latch tim ing high
15
0
1
CD_ B C K
CD_ LRCK
DA T A
C2 P 0
14 13 12 11 10 9
8
7
6
5
4
3
2
Invalid
0
15
0
1
14 13 12 11 10 9
8
7
6
5
4
3
2
In va lid
M S BLSB
MSBLS B
Up per (Right Channel)
Lower (Right Chann el)
Upper (Left Channel)
Lower (Left Cha nnel)
32-bit B C K , MS B First, Left C hann el L ow , C 2P 0 MS B F irst, D a ta latch tim ing lo w
15
0
1
CD_ B C K
CD_ LRCK
DA T A
C2 P 0
14 13 12 11 10 98765
4
3
2
Invalid
0
MSB
LS B
Lower (Left Channel)
Upper (Left Channe l)
Lower (Right Chan nel)
Upper (Righ t Chan nel)
24-bit B C K , MS B First, R ig ht C han nel L ow , C 2P 0 M S B F irst, D ata la tc h tim ing high
Left Channel
Righ t Channel
Right Ch annel
Le ft Channel
Left Channel
Righ t Channel
15
0
1
14 13 12 11 10 98765432
In va lid
MSB
LS B
15 14 13 12 11 10 9
8
7
6
5
Invalid
MSB
Upper (Left Channel)
Left Channel
CD_ B C K
CD_ LRCK
DA T A
C2 P 0
Invalid
0
LSB
M SB
Lower (Left Channel)
Upper (Left Channe l)
Lower (Right Chan nel)
Upper (Righ t Chan nel)
24-bit B C K , LS B F irst, R ight C hann el L ow , C 2P 0 MS B F irst, D a ta latch tim ing lo w
Left Channel
Righ t Channel
In va lid
LSB
MS B
Invalid
LSB
Upper (Left Channel)
Left Channel
015
114
13
12
11
10
9
8
7
6
5
4
3
20
15
114
13
12
11
10
9
8
7
6
5
4
3
2
01
10
9
8
7
6
5
4
3
2
15
0
1
CD_ B C K
CD_ LRCK
DA T A
14 13 12 11 10 98765
4
3
2
Invalid
0
MSB
LS B
2 4-bit B C K , M S B F irst, R ight C hanne l Low , D a ta latch tim ing high (N ote: no C 2P 0 for this fo r m at)
Left Channel
Righ t Channel
15
0
1
14 13 12 11 10 98765432
In va lid
MSB
LS B
15 14 13 12 11 10 9
8
7
6
5
Invalid
MSB
Left Channel
15
0
1
CD_ B C K
CD_ LRCK
DA T A
C2 P 0
14 13 12 11 10 98765432
0
MS B
LSB
Lower (Left Cha nnel)
Upper (Left Channel)
Lower (Right Channel)
Upper (Right Channel)
16-bit B C K , MS B First, Left C hann el L ow , C 2P 0 LS B Firs t, D ata la tch ti m in g high
Left Ch annel
Right Channel
15
0
1
14 13 12 11 10 9
8
7
6
5
4
3
2
MS B
L SB
15
0
1
14 13 12 11 10 98765432
MSB
L SB
Lower (Left Channel)
Upper (Left Channel)
Lower (Right Chan nel)
Upper (Right Chan nel)
Left Ch annel
Righ t Chan nel
15
0
1
14 13 12 11 10 9
8
7
6
5
4
3
2
MSB
LSB
15 14 13
MSB



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