CS98200 datasheet(34/60 Pages) CIRRUS

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DS581PP2

CS98200

Next Generation DVD Processor

5.12

Universal Asynchronous

Receiver/Transmitters (UARTs)

The UART performs serial-to-parallel conver-

sion on data characters received from a periph-

eral device and parallel-to-serial conversion on

data characters received from the host proces-

sor. Figure 22 shows RXD and TXD data trans-

fers over the UART interface.

The CS98200 has 2 UART interfaces based on a

NS16550-compatible design, which incorpo-

rates 16-byte transmit and receive FIFOs to en-

hance performance and throughput. As with

the 16650, it can operate in both FIFO-mode

(16550) or in the original non-FIFO mode

(16450). The main registers are identical in

structure to the NS16550, but some unused bits

have been enabled for added functionality.

The standard features are:

• Compatible with 16450 UART

• 16-byte transmit and receive FIFOs reduce

number of interrupts presented to CPU

• Generates and detects standard asynchronous

communication bits (start, stop and parity) to

and from serial data

• Independently controlled transmit, receive, line

status and data set interrupts

• Programmable baud rate generator (16 bit

divisor)

• Modem control interface (CTS, RTS, DSR, DTR,

RI and DCD)

• Fully programmable serial-interface

characteristics:

— 5, 6, 7 or 8 bit characters

— Even, odd or no-parity bit

generation/detection

— 1, 1½, or 2 stop bit generation

• False start bit detection

• Complete status reporting capabilities

• Line break generation and detection

• Internal loopback diagnostic mode

• Programmable trigger levels for FIFOs

• Selectable DMA signaling mode

• Prioritized interrupts

• Transmitter and receiver FIFO time-out

interrupts

Additional optimizations:

• Byte enable register allows transfer of up to 4

bytes in a single register write (only in FIFO

mode).

• External loopback diagnostic mode

• Separate baud clock input available

• Additional receiver error information

Note: If using separate baud clock, it must be less

than ½ frequency of the system clock,

otherwise, you must use the system clock.

RX D

TX D

Parity

D a ta B its (5 ~ 8 )

Start

Stop

Parity

D a ta B its (5 ~ 8 )

Start

Stop

Start

Figure 22. UART Data Transfer

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