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CS98200 Datasheet(PDF) 23 Page - Cirrus Logic |
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CS98200 Datasheet(HTML) 23 Page - Cirrus Logic |
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23 / 60 page ![]() DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 23 CS98200 Next Generation DVD Processor 2.2.9 Audio Output Interface Timing Figure 17 and Figure 16 illustrate the signal timing for the digital audio pins. Symbol Description Min Typ Max Unit taxper AUD_XCLK period (Input/Output)1, 2 13 - ns taxch AUD_XCLK High Time (Input/Output)1, 2 1.Values are guaranteed by design only 2.Active clock edge is programmable. Timing is referenced from active edge 40 50 % taxcl AUD_XCLK Low Time (Input/Output)1, 2 47 50 % tsdmo AUDO_BCK delay from AUD_XCLK output rise 10 tsdmi AUDO_BCK delay from AUD_XCLK input rise 20 taoper AUDO_BCK period (Output)1, 2 104 tlrds AUDO_LR delay from AUDO_BCK output rise -10 10 ns tadsm AUDO_D[3:0] delay from AUDO_BCK output rise -10 10 ns Table 7. Digital Audio Out Characteristics Figure 17. Digital Audio Out Timing Diagram AUDO_BCK(Output) AUD_XCLK(Input/Output) t sdm t axch AUDO_BCK(Output) AUDO_DO[3:0] (Output) AUDO_LR(Output) t lrds t adsm t axcl t axper t aoperl |
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