High = Power Good

PG

Low = Fault

(95%)

(93%)

(107%)

(105%)

10

LM60440, LM60430

SNVSBN5A – FEBRUARY 2020 – REVISED JUNE 2020

www.ti.com

Product Folder Links: LM60440 LM60430

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Power-Good Flag Output

The power-good flag function (PG output pin) of the LM604x0 can be used to reset a system microprocessor

whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as

current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation

for short excursions of the output voltage, such as during line and load transients. The timing parameters of the

trip the power-good flag. Power-good operation can best be understood by reference to Figure 1 and Figure 2.

Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to

the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during

normal operation of the power-good function.

The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic

not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN

low, power good remains valid as long as the input voltage is

≥ 2 V (typical). Limit the current into the power-

good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device

is enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any

transient currents that can occur when discharging a filter capacitor connected to this output.

Figure 1. Static Power-Good Operation