C

IN

VIN

SW

GND

KEEP

CURRENT

LOOP

SMALL

27

LM60440, LM60430

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SNVSBN5A – FEBRUARY 2020 – REVISED JUNE 2020

Product Folder Links: LM60440 LM60430

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Copyright © 2020, Texas Instruments Incorporated

Layout Guidelines (continued)

Figure 21. Current Loops with Fast Edges

11.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane

provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control

circuitry. The AGND and PGND pins must be connected to the ground planes using vias next to the bypass

capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected

directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching

frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be

constrained to one side of the ground planes. The other side of the ground plane contains much less noise and

must be used for sensitive routes.

Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat

dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1

oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout, provides low current

conduction impedance, proper shielding, and lower thermal resistance.