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MPC5673K Datasheet(PDF) 7 Page - NXP Semiconductors |
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MPC5673K Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 147 page ![]() Introduction MPC5675K Microcontroller Data Sheet, Rev. 8.1 NXP Semiconductors 7 • On-chip CAN/UART bootstrap loader • Capable of operating on a single 3.3 V voltage supply — 3.3 V-only modules: I/O, oscillators, flash memory — 3.3 V or 5 V modules: ADCs, supply to internal VREG — 1.8–3.3 V supply range: DRAM/PDI • Operating junction temperature range –40 to 150 °C 1.6 Feature details 1.6.1 High-performance e200z7d core processor • Dual 32-bit Power Architecture processor core • Loose or tight core coupling • NXP Variable Length Encoding (VLE) enhancements for code size footprint reduction • Thirty-two 64-bit general-purpose registers (GPRs) • Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB) • Branch processing unit • Fully pipelined load/store unit • 16 KB Instruction and 16 KB Data caches per core with line locking — Four way set associative — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data cache parity — Supports EDC for instruction cache • Vectored interrupt support • Signal processing engine 2 (SPE2) auxiliary processing unit (APU) operating on 64-bit general purpose registers • Floating point — IEEE 754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point • Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the MPC5675K • To reduce latency, long cycle time instructions are aborted upon interrupt requests • Extensive system development support through Nexus debug module 1.6.2 Crossbar Switch (XBAR) • 32-bit address bus, 64-bit data bus • Simultaneous accesses from different masters to different slaves (there is no clock penalty when a parked master accesses a slave) 1.6.3 Memory Protection Unit (MPU) Each master (eDMA, FlexRay, CPU) can be assigned different access rights to each region. |
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