MPC5673K datasheet(84/147 Pages) NXP

84 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 8.1

Electrical characteristics

NXP Semiconductors

6CS

D ADC input sampling capacitance

—

— 7.32

7CP1

D ADC input pin capacitance 1

—

2.5

8CP2

D ADC input pin capacitance 2

—

0.8

9RSW1

D Channel selection switch resistance

VREF range=4.5to5.5 V

—

1.0

VREF range=3.0to3.6 V

—

1.2

RAD

D Sample switching resistance

—

825

IINJ

T Current injection

Current injection on one ADC

input channel, different from

the converted one. Other

parameters stay within

specified limits as long as the

ADC supply stays within its

specified limits due to the

current injection.

–3

—

INL

P Integral non linearity

—

–3

—

LSB

DNL

P Differential non linearity6

—–1.0

—

LSB

OFS

T Offset error

—

–4

—

LSB

GNE

T Gain error

—

–4

—

LSB

TUE7

P Total unadjusted error

—

–6

—

LSB

TUE7

T Total unadjusted error with current injection

—

–6

—

LSB

SNR

T Signal-to-noise ratio

—

THD

T Total harmonic distortion

—

–72

—

21 SINAD T Signal-to-noise and distortion

—

22 ENOB

T Effective number of bits

—

10.5

—

bits

1 V

DD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.

2 AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

3 During the sample time the input capacitance C

S can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of

the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the

sample clock tADC_S depend on programming.

4 This parameter does not include the sample time t

ADC_S, but only the time for determining the digital result and the time

to load the result register with the conversion result.

5 See Figure 9.

6 No missing codes.

7 When operating the MPC5675K in a switched mode power supply configuration, the specifications for the ADCs under

worst case conditions can be upheld only through the use of averaging back-to-back samples. In the 257 package, 10

samples must be averaged when using ADC 0, 2, or 3. In the 473 package, 5 samples must be averaged. For ADC 1,

due to its close proximity to the PMC, the TUE spec must be increased to +/-10 counts, 10 samples of averaging must

be used in both packages, and the VDD_HV_PMU supply must be below 3.6 V. Better performance can be obtained

with lower VDD_HV_PMU supplies and higher VDD_HV_ADRx supplies. The ADC1 self test limit for the S2 algorithm

needs to be modified by the user to accommodate for the increased TUE limit of +/-10 counts when operating the device

in internal regulation mode. This can be accomplished by reading the current value from the test flash and subtracting

4 counts before storing the value to the ADC1 Self Test Analog Watchdog Register 2 (STAW2R).

Table 24. ADC conversion characteristics (continued)

No.

Symbol

Parameter

Conditions1

Min Typ Max Unit

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