MPC5673K datasheet(9/147 Pages) NXP

9 / 147 page

Introduction

MPC5675K Microcontroller Data Sheet, Rev. 8.1

NXP Semiconductors

1.6.7

External Bus Interface (EBI)

•

Available on 473-pin devices

•

Data and address options:

— 16-bit data and address (non-muxed)

— 32-bit data and address (bus-muxed)

•

MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable

to 26-bit address bus

•

Memory controller with support for various memory types

— Non-burst and burst mode SDR flash and SRAM

— Asynchronous/legacy flash and SRAM

•

Configurable bus speed modes

•

Support for 2 MB address space

•

Chip select and write/byte enable options as presented in the pin-muxing table in the “Signal Description” chapter of

the MPC5675K reference manual

•

Configurable wait states (via chip selects)

•

Optional automatic CLKOUT gating to save power and reduce EMI

1.6.8

On-chip flash memory

•

Up to 2 MB code flash memory with ECC

•

64 KB data flash memory with ECC

•

Censorship protection scheme to prevent flash content visibility

•

Multiple block sizes to support features such as boot block, operating system block, and EEPROM emulation

•

Read-while-write with multiple partitions

•

Parallel programming mode to support rapid end-of-line programming

•

Hardware programming state machine

1.6.9

Cache memory

•

Harvard architecture cache

•

16 KB instruction / 16 KB data

•

Four-way set-associative Harvard (instruction and data) 256-bit long cache

— Two 32-bit fetches per clock

— Eight-entry store buffer

— Way locking

— Supports tag and data cache parity

— Supports EDC for instruction cache

1.6.10

On-chip internal static RAM (SRAM)

•

Up to 512 KB general-purpose SRAM

•

ECC performs single-bit correction, double-bit error detection

— Address included in ECC checkbase

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