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MPC5673K Datasheet(PDF) 93 Page - NXP Semiconductors

Part # MPC5673K
Description  MPC5675K Microcontroller
PDF  147 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC5673K Datasheet(HTML) 93 Page - NXP Semiconductors

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Electrical characteristics
MPC5675K Microcontroller Data Sheet, Rev. 8.1
NXP Semiconductors
93
3.19
DRAM pad specifications
This section specifies the electrical characteristics of the DRAM pads. Please refer to the tables in Section 2.2, Pin descriptions,
for a cross reference between package pins and pad types.
DRAM pads feature list:
•
Driver
— Configurable to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half strength, DDR2 full
strength, and SDR modes.
— VDD_HV_DRAM range of
– 1.8 V nominal
– 2.5 V nominal
– 3.3 V nominal
•
Receiver
— Differential or pseudo-differential input buffer in all DRAM pads
— All inputs are tolerant up to their VDD_HV_DRAM absolute maximum rating
— Data and strobe pads can be configured to support four signal termination options
– Infinite/no termination
–50
Ω
–75
Ω
– 150
Ω
The electrical data provided in Section 3.19, DRAM pad specifications, applies to the pads listed in Table 43.
All three pad types can be configured to support SDR, DDR, DDR2 half and full strength, and LPDDR half and full strength
modes, according to Table 44.
Low
High
x
Outputs Disabled
High
Low
Low
Outputs Disabled
High
Low
High
Outputs drive high
High
High
Low
Normal Operation1
High
High
High
Normal Operation
1 Normal operation except no drive current and input buffer output is unknown. The pad
pre-drive circuitry will function normally but since VDD_HV_PDI is unpowered the outputs
will not drive high even though the output PMOS can be enabled.
Table 43. DRAM pads
Name
Voltage
Used For
Notes1
1 All pads can be configured to support LPDDR half strength, LPDDR full strength, DDR1, DDR2 half
strength, DDR2 full strength, and SDR.
DRAM ACC
1.62 V–3.6 V
I/O
Bidirectional DDR pad
DRAM CLK
1.62 V–3.6 V
O
Output only differential clock driver pad
DRAM DQ
1.62 V–3.6 V
I/O
Bidirectional DDR pad with integrated ODT
Table 42. Power sequence pin states for PDI pads
VDD_LV_COR
VDD_HV_IO
VDD_HV_PDI
Pad Function



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