MPC5673K datasheet(10/147 Pages) NXP

10 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 8.1

Introduction

NXP Semiconductors

1.6.11

DRAM controller

The DRAM controller (available only on 473-pin devices) is a multi-port controller that monitors incoming requests on the three

AHB slave ports and decides (at each rising clock edge) what command needs to be sent to the external DRAM.

The DRAM controller on this device supports the following types of memories:

•

Mobile DDR (mDDR)

•

DDR 1

•

DDR 2 (optional)

•SDR

The controller has the following features:

•

Optimized timing for 32-byte bursts and single read accesses on the AHB interface

•

Optimized timing for 8-byte and 16-byte bursts on the DRAMC interface

•

Supports priority elevation on the slave ports for single accesses

•

16-bit wide DRAM interface

•

One chip select (CS)

•

mDDR memory controller

— 16-bit external interface

— Address range up to 8 MB

1.6.12

Boot Assist Module (BAM)

•

Enables booting via serial mode (FlexCAN, LINFlex)

•

Handles static mode in case of an erroneous boot procedure

•

Implemented in 8 KB ROM

•

Supports Lock Step Mode (LSM) and Decoupled Parallel Mode (DPM)

1.6.13

Parallel Data Interface (PDI)

•

Support for external ADC and CMOS image sensors

•

Parallel interface operation up to MCU system bus frequency

•

Selectable data capture from rising or falling edge

•

Receive FIFO with adjustable trigger thresholds

•

Data width for 8, 10, 12, 14, and 16 bits

•

Data Packing Unit to pack input data on 64-bit words — data packed on 8- or 16- bit boundary, depending on input

data width

•

Binary increasing channel select that allows as many as eight channels to be selected

•

Frame synchronization through Vsync, Hsync, PIXCLK

1.6.14

Deserial Serial Peripheral Interface (DSPI) modules

•

Three serial peripheral interfaces

— Full duplex communication ports with interrupt and eDMA request support

— Support for all functional modes from QSPI submodule of QSMCM (MPC5xx family)

— Support for queues in RAM

— Six chip selects, expandable to 64 with external demultiplexers

— Programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis

MPC5673K Datasheet(PDF) 10 Page - NXP Semiconductors

MPC5673K Datasheet(HTML) 10 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL