DS3172 datasheet(188/232 Pages) DALLAS

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12.9.4 Receive G.751 E3 Register Map

The receive G.751 E3 utilizes eight registers.

Table 12-26. Receive G.751 E3 Framer Register Map

Address

(1,3,5,7)20h

E3G751.RCR

E3 G.751 Receive Control Register

(1,3,5,7)22h

Reserved

(1,3,5,7)24h

E3G751.RSR1

E3 G.751 Receive Status Register #1

(1,3,5,7)26h

E3G751.RSR2

E3 G.751 Receive Status Register #2

(1,3,5,7)28h

E3G751.RSRL1

E3 G.751 Receive Status Register Latched #1

(1,3,5,7)2Ah E3G751.RSRL2

E3 G.751 Receive Status Register Latched #2

(1,3,5,7)2Ch E3G751.RSRIE1

E3 G.751 Receive Status Register Interrupt Enable #1

(1,3,5,7)2Eh E3G751.RSRIE2

E3 G.751 Receive Status Register Interrupt Enable #2

(1,3,5,7)30h

Reserved

(1,3,5,7)32h

Reserved

(1,3,5,7)34h

E3G751.RFECR

E3 G.751 Receive Framing Error Count Register

(1,3,5,7)36h

Reserved

(1,3,5,7)38h

Reserved

(1,3,5,7)3Ah

Reserved

(1,3,5,7)3Ch

Unused

(1,3,5,7)3Eh

Unused

12.9.4.1 Register Bit Descriptions

E3G751.RCR

E3 G.751 Receive Control Register

(1,3,5,7)20h

Bit #

Name

Reserved

DLS

MDAISI

AAISD

ECC

FECC1

FECC0

Default

Bit #

Name

RAILE

RAILD

RAIOD

RAIAD

ROMD

LIP1

LIP0

FRSYNC

Default

Bit 13: Receive FEAC Data Link Source (DLS) – When 0, the receive FEAC controller will be sourced from the N

bit. When 1, the receive FEAC controller will be sourced from the A bit.

Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.

When 1, manual downstream AIS insertion is enabled.

Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition

will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause

downstream AIS to be inserted.

Bit 10: Error Count Control (ECC) – When 0, framing errors will not be counted if an OOF or AIS condition is

present. When 1, framing errors will be counted regardless of the presence of an OOF or AIS condition.

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