DS3172 datasheet(189/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events

that are counted.

00 = count OOF occurrences (counted regardless of the setting of the ECC bit)..

01 = count each bit error in the FAS (up to 10 per frame).

10 = count frame alignment signal (FAS) errors (up to one per frame).

11 = reserved

Bit 7: Receive Alarm Indication on LOF Enable (RAILE) – When 0, an LOF condition does not affect the receive

alarm indication signal (RAI). When 1, an LOF condition will cause the transmit E3 A bit to be set to one if transmit

automatic RAI is enabled.

Bit 6: Receive Alarm Indication on LOS Disable (RAILD) – When 0, an LOS condition will cause the transmit E3

A bit to be set to one if transmit automatic RAI is enabled. When 1, an LOS condition does not affect the RAI

signal.

Bit 5: Receive Alarm Indication on OOF Disable (RAIOD) – When 0, an OOF condition will cause the transmit

E3 A bit to be set to one if transmit automatic RAI is enabled. When 1, an OOF condition does not affect the RAI

signal.

Bit 4: Receive Alarm Indication on AIS Disable (RAIAD) – When 0, an AIS condition will cause the transmit E3

A bit to be set to one if transmit automatic RAI is enabled. When 1, an AIS condition does not affect the RAI signal.

Bit 3: Receive Overhead Masking Disable (ROMD) – When 0, the E3 overhead positions in the outgoing E3

payload will be marked as overhead by RDENn. When 1, the E3 overhead positions in the outgoing E3 payload will

be marked as data by RDENn.

Bits 2 to 1: LOF Integration Period (LIP[1:0]) – These two bits determine the OOF integration period for

declaring LOF.

00 = OOF is integrated for 3 ms before declaring LOF

01 = OOF is integrated for 2 ms before declaring LOF.

10 = OOF is integrated for 1 ms before declaring LOF

11 = LOF is declared at the same time as OOF

Bit 0: Force Framer Resynchronization (FRSYNC) – A 0 to 1 transition forces an OOF condition at the FAS

check. This bit must be cleared and set to one again to force another resynchronization

E3G751.RSR1

E3 G.751 Receive Status Register #1

(1,3,5,7)24h

Bit #

Name

Reserved

RUA1

Bit #

Name

RAB

RNB

LOF

RDI

AIS

OOF

LOS

Bit 8: Receive Unframed All 1’s (RUA1) – When 0, the receive frame processor is not in a receive unframed all

1’s (RUA1) condition. When 1, the receive frame processor is in an RUA1 condition.

Bit 7: Receive A Bit (RAB) – This bit is the integrated A bit extracted from the E3 frame.

Bit 6: Receive N Bit (RNB) – This bit is the integrated N bit extracted from the E3 frame.

Bit 4: Loss Of Frame (LOF) – When 0, the receive frame processor is not in a loss of frame (LOF) condition.

When 1, the receive frame processor is in an LOF condition.

Bit 3: Remote Alarm Indication (RDI) – This bit indicates the current state of the remote alarm indication (RDI).

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