DS3172 datasheet(194/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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Bits 9 to 8: Transmit NR Byte Control (TNRC[1:0]) – These two bits control the source of the NR byte.

00 = all ones.

01 = transmit from the HDLC controller.

10 = transmit from the FEAC controller.

11 = NR byte register.

Note: If TNRC[1:0] is 01 and TGCC is 0, both the NR byte and GC byte will carry the same transmit HDLC

controller (eight bits per frame period), however, the NR byte and GC byte in the same frame may or may not be

equal.

Bit 5: Transmit REI Error (TFEBE) – When automatic REI generation is defeated (AFEBED = 1), this bit is

inserted into the second bit of the MA byte.

Bit 4: Automatic REI Defeat (AFEBED) – When 0, the REI is automatically generated based upon the transmit

remote error indication (TREI) signal. When 1, the REI is inserted from the register bit TFEBE.

Bit 3: Transmit RDI Alarm (TRDI) – When automatic RDI generation is defeated (ARDID = 1), this bit is inserted

into the first bit of the MA byte.

Bit 2: Automatic RDI Defeat (ARDID) – When 0, the RDI is automatically generated based upon the received E3

alarms. When 1, the RDI is inserted from the register bit TRDI.

Bit 1: Transmit Frame Generation Control (TFGC) – When this bit is zero, the Transmit Frame Processor frame

generation is enabled. The E3 overhead positions in the incoming E3 payload will be overwritten with the internally

generated DS3 overhead. When this bit is one, the Transmit Frame Processor frame generation is disabled. The

E3 overhead positions in the incoming E3 payload will be passed through to error insertion. Note: The E3 overhead

periods can still be overwritten by overhead insertion.

Bit 0: Transmit Alarm Indication Signal (TAIS) – When 0, the normal signal is transmitted. When 1, the E3

output data stream is forced to all ones (AIS).

E3G832.TEIR

E3 G.832 Transmit Error Insertion Register

(1,3,5,7)1Ah

Bit #

Name

Reserved

CFBEIE

FBEI

Default

Bit #

Name

PBEE

CPEIE

PEI

FEIC1

FEIC0

FEI

TSEI

MEIMS

Default

Bit 9: Continuous Remote Error Indication Error Insertion Enable (CFBEIE) – When 0, single remote error

indication (REI) error insertion is enabled. When 1, continuous REI error insertion is enabled, and REI errors will be

transmitted continuously if FEBI is high.

Bit 8: Remote Error Indication Error Insertion Enable (FBEI) – When 0, REI error insertion is disabled. When 1,

REI error insertion is enabled.

Bit 7: Parity Block Error Enable (PBEE) – When 0, a parity error is generated by inverting a single bit in the EM

byte. When 1, a parity error is generated by inverting all eight bits in the EM byte.

Bit 6: Continuous Parity Error Insertion Enable (CPEIE) – When 0, single parity (BIP-8) error insertion is

enabled. When 1, continuous parity error insertion is enabled, and parity errors will be transmitted continuously if

PEI is high.

Bit 5: Parity Error Insertion Enable (PEI) – When 0, parity error insertion is disabled. When 1, parity error

insertion is enabled.

DS3172 Datasheet(PDF) 194 Page - Dallas Semiconductor

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