DS3172 datasheet(197/232 Pages) DALLAS

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an OOF or AIS condition is terminated, and the next E3 frame. When 1, framing errors, parity errors, and REI

errors will be counted regardless of the presence of an OOF or AIS condition.

Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events

that are counted.

00 = count OOF occurrences (counted regardless of the setting of the ECC bit)..

01 = count each bit error in FA1 and FA2 (up to 16 per frame).

10 = count frame alignment word (FA1 and FA2) errors (up to one per frame).

11 = count FA1 byte errors and FA2 byte errors (up to 2 per frame).

Bit 7: Receive Defect Indication on LOF Enable (RDILE) – When 0, an LOF condition does not affect the receive

defect indication signal (RDI). When 1, an LOF condition will cause the transmit E3 RDI bit to be set to one if

transmit automatic RDI is enabled.

Bit 6: Receive Defect Indication on LOS Disable (RDILD) – When 0, an LOS condition will cause the transmit E3

RDI bit to be set to one if transmit automatic RDI is enabled. When 1, an LOS condition does not affect the RDI

signal.

Bit 5: Receive Defect Indication on OOF Disable (RDIOD) – When 0, an OOF condition will cause the transmit

E3 RDI bit to be set to one if transmit automatic RDI is enabled. When 1, an OOF condition does not affect the RDI

signal.

Bit 4: Receive Defect Indication on AIS Disable (RDIAD) – When 0, an AIS condition will cause the transmit E3

RDI bit to be set to one if transmit automatic RDI is enabled. When 1, an AIS condition does not affect the RDI

signal.

Bit 3: Receive Overhead Masking Disable (ROMD) – When 0, the E3 overhead positions in the outgoing E3

payload will be marked as overhead by RDENn. When 1, the E3 overhead positions in the outgoing E3 payload will

be marked as data by RDENn.

Bits 2 to 1: LOF Integration Period (LIP[1:0]) – These two bits determine the OOF integration period for

declaring LOF.

00 = OOF is integrated for 3 ms before declaring LOF.

01 = OOF is integrated for 2 ms before declaring LOF.

10 = OOF is integrated for 1 ms before declaring LOF.

11 = LOF is declared at the same time as OOF.

Bit 0: Force Framer Resynchronization (FRSYNC) – A 0 to 1 transition forces. an OOF condition at the next

framing word check. This bit must be cleared and set to one again to force another resynchronization.

E3G832.RMACR

E3 G.832 Receive MA Byte Control Register

(1,3,5,7)22h

Bit #

Name

Default

Bit #

Name

EPT2

EPT1

EPT0

TIED

Default

Bits 3 to 1: Expected Payload Type (EPT[2:0]) – These three bits contain the expected value of the payload

type.

Bit 0: Timing Source Indicator Bit Extraction Disable (TIED) – When 0, the four timing source indications bits

are extracted from the last three bits of the MA byte (MA[6:8]), and stored in a register. When 1, timing source

indicator bit extraction is disabled, and the last three bits of the MA byte are integrated and stored in a register.

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