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DS3172 Datasheet(PDF) 196 Page - Dallas Semiconductor |
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DS3172 Datasheet(HTML) 196 Page - Dallas Semiconductor |
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196 / 232 page  DS3171/DS3172/DS3173/DS3174 196 of 232 12.9.6 Receive G.832 E3 Register Map The receive G.832 E3 utilizes thirteen registers. Table 12-28. Receive G.832 E3 Framer Register Map Address Register Register Description (1,3,5,7)20h E3G832.RCR E3 G.832 Receive Control Register (1,3,5,7)22h E3G832.RMACR E3 G.832 Receive MA Byte Control Register (1,3,5,7)24h E3G832.RSR1 E3 G.832 Receive Status Register #1 (1,3,5,7)26h E3G832.RSR2 E3 G.832 Receive Status Register #2 (1,3,5,7)28h E3G832.RSRL1 E3 G.832 Receive Status Register Latched #1 (1,3,5,7)2Ah E3G832.RSRL2 E3 G.832 Receive Status Register Latched #2 (1,3,5,7)2Ch E3G832.RSRIE1 E3 G.832 Receive Status Register Interrupt Enable #1 (1,3,5,7)2Eh E3G832.RSRIE2 E3 G.832 Receive Status Register Interrupt Enable #2 (1,3,5,7)30h E3G832.RMABR E3 G.832 Receive MA Byte Register (1,3,5,7)32h E3G832.RNGBR E3 G.832 Receive NR and GC Byte Register (1,3,5,7)34h E3G832.RFECR E3 G.832 Receive Framing Error Count Register (1,3,5,7)36h E3G832.RPECR E3 G.832 Receive Parity Error Count Register (1,3,5,7)38h E3G832.RFBER E3 G.832 Receive Remote Error Indication Count Register (1,3,5,7)3Ah -- Reserved (1,3,5,7)3Ch -- Unused (1,3,5,7)3Eh -- Unused 12.9.6.1 Register Bit Descriptions Register Name: E3G832.RCR Register Description: E3 G.832 Receive Control Register Register Address: (1,3,5,7)20h Bit # 15 14 13 12 11 10 9 8 Name Reserved PEC DLS MDAISI AAISD ECC FECC1 FECC0 Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Name RDILE RDILD RDIOD RDIAD ROMD LIP1 LIP0 FRSYNC Default 0 0 0 0 0 0 0 0 Bit 14: Parity Error Count (PEC) – When 0, BIP-8 block errors (EM byte) are detected (no more than one per frame). When 1, BIP-8-bit errors are detected (up to 8 per frame). Bit 13: Receive HDLC Data Link Source (DLS) – When 0, the receive HDLC data link will be sourced from the GC byte. When 1, the receive HDLC data link will be sourced from the NR byte. Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled. When 1, manual downstream AIS insertion is enabled. Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause downstream AIS to be inserted. Bit 10: Error Count Control (ECC) – When 0, framing errors, parity errors, and REI errors will not be counted if an OOF or AIS condition is present. Parity errors and REI errors will also not be counted during the E3 frame in which |
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