 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VR4102 Datasheet(PDF) 220 Page - NEC |
|
|
|||||||||||||||||||||||||||||
VR4102 Datasheet(HTML) 220 Page - NEC |
|
|
220 / 701 page  CHAPTER 8 CACHE MEMORY 220 8.6 CACHE DATA INTEGRITY The D- and I-cache data RAM arrays are protected by parity (byte parity for D-cache, word parity for I-cache). D- and I-cache tag RAM arrays are also protected by parity. These parity bits are checked for errors on every cache read access. Cache error exception occurs if the CPU core encounters a parity error during an instruction cache access, a data cache access, or memory read access. The CacheErr register indicates the source of the error. Figure 8-8 to Figure 8-22 shows the parity generation and checking operations for various cache accesses. Figure 8-8. Data flow on Instruction Fetch OK, DE = 1 or ERL = 1 Start Error TagParity Cache Error Exception TagCheck Refill Desigerd Data Parity Miss or Invalid (See Figure 8-21) OK, DE = 1 or ERL = 1 TagCheck Data Fetch END Cache Error Exception Hit Error |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
