VR4102 datasheet(217/701 Pages) NEC

217 / 701 page

CHAPTER 8 CACHE MEMORY

217

8.3 CACHE OPERATIONS

As described earlier, caches provide fast temporary data storage, and they make the speedup of memory

accesses transparent to the user. In general, the CPU core accesses cache-resident instructions or data through

the following procedure:

1. The CPU core, through the on-chip cache controller, attempts to access the next instruction or data in the

appropriate cache.

2. The cache controller checks to see if this instruction or data is present in the cache.

— If the instruction/data is present, the CPU core retrieves it. This is called a cache hit.

— If the instruction/data is not present in the cache, the cache controller must retrieve it from memory. This is

called a cache miss.

3. The CPU core retrieves the instruction/data from the cache and operation continues.

It is possible for the same data to be in two places (main memory and cache) simultaneously. This data is kept

consistent through the use of a write-back methodology; that is, modified data is not written back to memory until the

cache line is to be replaced.

Instruction and data cache line replacement operations are described in the following sections.

8.3.1 Cache Write Policy

The VR4100 CPU core manages its data cache by using a write-back policy; that is, it stores write data into the

cache, instead of writing it directly to memory

Note. Some time later this data is independently written into memory. In

the VR4102 implementation, a modified cache line is not written back to the main memory until the cache line is to be

replaced either in the course of satisfying a cache miss, or during the execution of a write-back CACHE instruction.

When the CPU core writes a cache line back to the main memory, it does not ordinarily retain a copy of the cache

line, and the state of the cache line is changed to invalid.

Note

Write-through cache policy performs the function contrary to the write-back policy. Data written into memory

is also written into cache simultaneously.

VR4102 Datasheet(PDF) 217 Page - NEC