VR4102 datasheet(214/701 Pages) NEC

214 / 701 page

CHAPTER 8 CACHE MEMORY

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The VR4100 CPU core has two on-chip caches: one holds instructions (the instruction cache), the other holds

data (the data cache). The instruction and data caches can be read in one PClock cycle.

Data writes are pipelined and can complete at a rate of one per PClock cycle. In the first stage of the cycle, the

store address is translated and the tag is checked; in the second stage, the data is written into the data RAM.

8.2 CACHE ORGANIZATION

This section describes the organization of the on-chip data and instruction caches. Figure 8-2 provides a block

diagram of the VR4100 CPU core cache and memory model.

Figure 8-2. Cache Support

VR4100 CPU core

Cache controller

I-cache

D-cache

Caches

Main memory

I-cache:

Instruction cache

D-cache: Data cache

(1) Cache Line Lengths

A cache line is the smallest unit of information that can be fetched from main memory for the cache, and that is

represented by a single tag.

The line size for the instruction/data cache is 4 words (16 bytes).

For cache tag, refer to 8.2.1 and 8.2.1.

(2) Cache Sizes

The instruction cache in the VR4100 CPU core is 4 Kbytes; the data cache is 1 Kbytes.

8.2.1 Organization of the Instruction Cache (I-Cache)

Each line of I-cache data (although it is actually an instruction, it is referred to as data to distinguish it from its tag)

has an associated 24-bit tag that contains a 22-bit physical address, a single Valid bit, and a single Parity bit. Word

parity is used on I-cache data (1 bit of parity per word).

The VR4100 CPU core I-cache has the following characteristics:

— direct-mapped

— indexed with a virtual address

— checked with a physical tag

— organized with a 4-word (16-byte) cache line.

Figure 8-3 shows the format of a 4-word (16-byte) I-cache line.

VR4102 Datasheet(PDF) 214 Page - NEC