VR4102 datasheet(211/701 Pages) NEC

211 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

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(4) Hibernate Mode

When the HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During

Hibernate mode, the processor stops supplying clocks to all units. The register and cache contents are retained

and output of TClock and MasterOut is stopped. The processor remains in Hibernate mode until the POWER

pin is asserted, a WakeUpTimer interrupt occurs, DCD# pin is asserted, or GPIO[3] is asserted, at which the

processor returns to Fullspeed mode.

Power consumption during Hibernate mode is about 0 W (it does not go completely to 0 W due to the existence

of a 32.768-kHz oscillator, on-chip peripheral units that operate at 32.768 kHz, or DRAM self refresh).

7.4.2 Privilege Mode

The VR4102 supports three system modes: kernel expanded addressing mode, supervisor expanded addressing

mode, and user expanded addressing mode. These three modes are described below.

(1) Kernel Expanded Addressing Mode

When the Status register’s KX bit has been set, an expanded TLB miss exception vector is used when a TLB

miss occurs for the kernel address. While in kernel mode, the MIPS III operation code can always be used,

regardless of the KX bit.

(2) Supervisor Expanded Addressing Mode

When the Status register’s SX bit has been set, the MIPS III operation code can be used when in supervisor

mode and an expanded TLB miss exception vector is used when a TLB miss occurs for the supervisor address.

(3) User Expanded Addressing Mode

When the Status register’s UX bit has been set, the MIPS III operation code can be used when in user mode,

and an expanded TLB miss exception vector is used when a TLB miss occurs for the user address. When this

bit is cleared, the MIPS I and II operation codes can be used, as can 32-bit virtual addresses.

7.4.3 Reverse Endian

When the Status register’s RE bit has been set, the endian ordering is reversed to adopt the user software’s

perspective. However, the RE bit of the Status register must be set to 0 since the VR4102 supports the little-endian

order only.

7.4.4 Bootstrap Exception Vector (BEV)

The BEV bit is used to generate an exception during operation testing (diagnostic testing) of the cache and main

memory system. This bit is automatically set to 1 after reset or NMI exception.

When the Status register’s BEV bit has been set, the address of the TLB miss exception vector is changed to the

virtual address 0xFFFF FFFF BFC0 0200 and the ordinary execution vector is changed to address 0xFFFF FFFF

BFC0 0380.

When the BEV bit is cleared, the TLB miss exception vector’s address is changed to 0xFFFF FFFF 8000 0000

and the ordinary execution vector is changed to address 0xFFFF FFFF 8000 0180.

VR4102 Datasheet(PDF) 211 Page - NEC