VR4102 datasheet(207/701 Pages) NEC

207 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

207

7.3 RESET OF THE CPU CORE

This section describes the reset sequence of the VR4100 CPU core. For details about factors of reset or reset of

the whole VR4102, refer to 7.1 and Chapter 15.

7.3.1 Cold Reset

In the VR4102, a cold reset sequence is executed in the CPU core in the following cases:

x RTC reset

x RSTSW reset

x Deadman’s SW shutdown

x Software shutdown

x HAL Timer shutdown

x Battery low shutdown

x Battery lock release shutdown

A Cold Reset completely initializes the CPU core, except for the following register bits.

x The TS and SR bits of the Status register are cleared to 0.

x The ERL and BEV bits of the Status register are set to 1.

x The upper limit value (31) is set in the Random register.

x The Wired register is initialized to 0.

x Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are undefined.

x The values of the other registers are undefined.

Once power to the processor is established, the ColdReset# (internal) and the Reset# (internal) signals are

asserted and a Cold Reset is started. After approximately 2 ms assertion, the ColdReset# signal is deasserted

synchronously with MasterOut. Then the Reset# signal is deasserted synchronously with MasterOut, and the Cold

Reset is completed.

Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted,

the CPU core branches to the Reset exception vector and begins executing the reset exception code.

VR4102 Datasheet(PDF) 207 Page - NEC