VR4102 datasheet(205/701 Pages) NEC

205 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

205

7.2 POWERON SEQUENCE

The factors that cause the VR4102 to switch from hibernate mode or shutdown mode to full speed mode are

called power-on factors. There are four power-on factors: assertion of the POWERON pin, assertion of the DCD#

pin, activation of the wakeup timer, and assertion of the GPIO pins (GPIO[3..0], GPIO[12..9]). When an activation

factor occurs, the VR4102 asserts the POWERON pin, then provides notification to external agents that the VR4102

is ready for power-on. Three RTC clocks after the POWERON pin is asserted, the VR4102 checks the state of the

BATTINH/BATTINT# pin. If the BATTINH/BATTINT# pin’s state is low, the POWERON pin is deasserted one RTC

clock after the BATTINH/BATTINT# pin check is completed, then the VR4102 is not activated.

If the

BATTINH/BATTINT# pin’s state is high, the POWERON pin is deasserted three RTC clocks after the

BATTINH/BATTINT# pin check is completed, then the MPOWER pin is asserted and the VR4102 is activated.

Figure 7-6 shows a timing chart of VR4102 activation and Figure 7-7 shows a timing chart of when activation fails

due to the BATTINH/BATTINT# pin’s “low” state.

For details of poweron sequence according to each power-on factor, refer to chapter 15.

VR4102 Datasheet(PDF) 205 Page - NEC