VR4102 datasheet(208/701 Pages) NEC

208 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

208

7.3.2 Soft Reset

Caution

Soft Reset is not supported in the present VR4102.

A Soft Reset initializes the CPU core without affecting the clocks; in other words, a Soft Reset is a logic reset. In a

Soft Reset, the CPU core retains as much state information as possible; all state information except for the following

is retained:

x The TS bit of the Status register is cleared to 0.

x The SR, ERL and BEV bits of the Status register are set to 1.

x The Count register is initialized to 0.

x The IP7 bit of the Cause register is cleared to 0.

x Any Interrupts generated on the SysAD bus are cleared.

x NMI is cleared.

x The Config register is initialized.

A Soft Reset is started by assertion of the Reset# signal, and is completed at the deassertion of the Reset# signal

synchronized with MasterOut. In general, data in the CPU core is preserved for debugging purpose.

Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted,

the CPU core branches to the Reset exception vector and begins executing the reset exception code.

VR4102 Datasheet(PDF) 208 Page - NEC