VR4102 datasheet(210/701 Pages) NEC

210 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

210

7.4 VR4102 PROCESSOR MODES

The VR4102 supports various modes, which can be selected by the user. The CPU core mode is set each time a

write occurs in the Status register and Config register. The on-chip peripheral unit mode is set by writing to the I/O

This section describes the CPU core’s operation modes. For operation modes of on-chip peripheral units, see the

chapters describing the various units.

7.4.1 Power Modes

The VR4102 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode.

(1) Fullspeed Mode

This is the normal operation mode.

The VR4102’s default status sets operation under Fullspeed mode. After the processor is reset, the VR4102

returns to Fullspeed mode.

(2) Standby Mode

When a STANDBY instruction has been executed, the processor can be set to Standby mode. During Standby

mode, all of the internal clocks in the CPU core except for the timer and interrupt clocks are held at high level.

The peripheral units all operate as they do during Fullspeed mode.

This means that DMA operations are

enabled during Standby mode.

When the STANDBY instruction completes the WB stage, the VR4102 remains idle until the SysAD internal bus

enters the idle state.

Next, the clocks in the CPU core are shut down and pipeline operation is stopped.

However, the PLL, timer, and interrupt clocks continue to operate, as do the internal bus clocks (TClock and

MasterOut).

During Standby mode, the processor is returned to Fullspeed mode if any interrupt occurs, including a timer

interrupt that occurs internally.

(3) Suspend Mode

When the SUSPEND instruction has been executed, the processor can be set to Suspend mode.

During

Suspend mode, the processor stalls the pipeline and supplying all of the internal clocks in the CPU core except

for PLL timer and interrupt clocks are stopped. The VR4102 stops supplying TClock to peripheral units.

Accordingly, during Suspend mode peripheral units can only be activated by a special interrupt unit (DCD#

control, etc.). While in this mode, the register and cache contents are retained.

When the SUSPEND instruction completes the WB stage, the VR4102 switches the DRAM to self refresh mode

and then waits for the SysAD internal bus to enter the idle state. Next, the clocks in the CPU core are shut down

and pipeline operation is stopped. The VR4102 then stops supplying TClock to peripheral units. However, the

PLL, timer, and interrupt clocks continue to operate, as do the MasterOut.

The processor remains in Suspend mode until an interrupt is received, at which time it returns to Fullspeed

mode.

VR4102 Datasheet(PDF) 210 Page - NEC