VR4102 datasheet(212/701 Pages) NEC

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VR4102 Datasheet(PDF) 212 Page - NEC

212 / 701 page

CHAPTER 7 INITIALIZATION INTERFACE

212

7.4.5 Cache Error Check

When the Status register’s CE bit has been set, the contents of the PErr register can be written to the data

cache’s parity bit instead of the parity generated by the STORE instruction. If the CACHE instruction’s “Fill” option is

executed, the contents of the PErr register can be written to the instruction cache’s parity bit instead of the

instruction parity.

7.4.6 Parity Error Prohibit

When the Status register’s DE bit has been set, the processor does not issue any cache parity error exceptions.

7.4.7 Interrupt Enable (IE)

When the Status register’s IE bit has been cleared, no interrupts can be received except for reset interrupts and

nonmaskable interrupts.

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