VR4102 datasheet(215/701 Pages) NEC

215 / 701 page

CHAPTER 8 CACHE MEMORY

215

Figure 8-3. Cache Line Format

PTag

DataP

Data

DataP

Data

DataP

Data

DataP

Data

PTag

Physical tag

(bits 31 to 10 of the physical address)

When a tag is specified by the Cache

instruction, however, the high-order 20

bits are used.

Valid bit

Even parity for the Ptag and V bit

Data

I-cache data

DataP

Even parity for the data

(1-bit parity for 4-byte data)

8.2.2 Organization of the Data Cache (D-Cache)

Each line of D-cache data has an associated 26-bit tag that contains a 22-bit physical address, a Valid bit, a

Parity bit, a Write-back bit, and a parity bit for Write-back.

The VR4100 CPU core D-cache has the following characteristics :

— write-back

— direct-mapped

— indexed with a virtual address

— checked with a physical tag

— organized with a 4-word (16-byte) cache line.

Figure 8-4 shows the format of a 4-word (16-byte) D-cache line.

Figure 8-4. Data Cache Line Format

W’

DataP

Data

DataP

Data

PTag

Physical tag

(bits 31 to 10 of the physical address)

Valid bit

Even parity for the Ptag and V bit

Write-back bit

(set if cache line has been written)

W’

Even parity for the write-back bit

Data

D-cache data

DataP

Even parity for the data (1-bit parity for

4-byte data)

PTag

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