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VR4102 Datasheet(PDF) 268 Page - NEC |
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VR4102 Datasheet(HTML) 268 Page - NEC |
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268 / 701 page  CHAPTER 10 BCU (BUS CONTROL UNIT) 268 10.5.6 Bus Hold Caution The BUSCLK signal is fixed at low level during execution of the SUSPEND instruction. Consequently, while the SUSPEND instruction is being executed, the bus is being used by an external master device and cannot be used for BUSCLK. Figure 10-26. Bus Hold in Fullspeed Mode (a) Transition to Bus Hold from Ordinary Operation TClock(Internal) MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 BUSCLK (b)Transition to Ordinary Operation from Bus Hold TClock(Internal) MasterOut(Internal) HLDRQ# HLDACK# Note 1 Note 2 BUSCLK Notes 1. UUCAS#/MRAS[3]#, ULCAS#/MRAS[2]#, MRAS[1..0]#, UCAS#, LCAS# 2. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD[25..0], DATA[15..0], DATA[31..16]/GPIO[31..16] (in 32-bit data bus mode) Remark The dotted lines indicate high impedance. |
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