VR4102 datasheet(281/701 Pages) NEC

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CHAPTER 12 DCU (DMA CONTROL UNIT)

This chapter describes the DCU register’s operations and settings.

12.1 GENERAL

The DCU register is used for DMA control. Specifically, it controls acknowledgment from the BCU that handles

bus arbitration and DMA requests from the on-chip peripheral I/O units (AIU and FIR).

It also controls DMA

enable/prohibit settings.

12.2 DMA PRIORITY CONTROL

When a conflict occurs between DMA requests sent from on-chip peripheral I/O units, the following priority levels

are used to resolve the conflict. These priority levels cannot be changed.

Table 12-1. DMA Priority Levels

Priority level

Type of DMA operation

High

Audio input (recording)

Audio output (playback)

Low

FIR transmission/reception

12.3 REGISTER SET

The DCU register set is described below.

Table 12-2. DCU Registers

Address

R/W

Function

0x0B00 0040

R/W

DMARSTREG

DMA Reset Register

0x0B00 0042

DMAIDLEREG

DMA Idle Register

0x0B00 0044

R/W

DMASENREG

DMA Sequencer Enable Register

0x0B00 0046

R/W

DMAMSKREG

DMA Mask Register

0x0B00 0048

R/W

DMAREQREG

DMA Request Register

0x0B00 004A

R/W

TDREG

Transfer Direction Register

These registers are described in detail below.

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