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VR4102 Datasheet(PDF) 285 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 285 Page - NEC

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CHAPTER 12 DCU (DMA CONTROL UNIT)
285
12.3.4 DMAMSKREG (0x0B00 0046)
Bit
D15
D14
D13
D12
D11
D10
D9
D8
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
R
RR
RRR
R
R
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
D7
D6D5
D4D3D2
D1
D0
Name
Reserved
Reserved
Reserved
Reserved
DMAMSKAIN
DMAMSK
AOUT
Reserved
DMAMSK
FOUT
R/W
R
R
R
R
R/W
R/W
R
R/W
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
D[15..4]
Reserved
Write 0 when writing. 0 is returned after a read.
D[3]
DMAMSKAIN
Audio input DMA transfer enable/prohibit
1 : Enable
0 : Prohibit
D[2]
DMAMSKAOUT
Audio output DMA transfer enable/prohibit
1 : Enable
0 : Prohibit
D[1]
Reserved
Write 0 when writing. 0 is returned after a read.
D[0]
DMAMSKFOUT
FIR transmission DMA transfer enable/prohibit
1 : Enable
0 : Prohibit
This register is used to enable/prohibit various types of DMA transfers.
The DMA transfer enable bits should be set when the units that receive DMA service have been stopped or when
there are no pending DMA requests. If any of the above bits are set to a unit while a DMA request is pending for that
unit, the CPU’s operation will be undefined.



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