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VR4102 Datasheet(PDF) 286 Page - NEC |
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VR4102 Datasheet(HTML) 286 Page - NEC |
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286 / 701 page ![]() CHAPTER 12 DCU (DMA CONTROL UNIT) 286 12.3.5 DMAREQREG (0x0B00 0048) Bit D15 D14 D13 D12 D11 D10 D9 D8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit D7 D6D5 D4D3D2 D1 D0 Name Reserved Reserved Reserved Reserved DRQAIN DRQAOUT Reserved DRQFOUT R/W R RR RRR R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Bit Name Function D[15..4] Reserved Write 0 when writing. 0 is returned after a read. D[3] DRQAIN Audio input DMA transfer request 1 : Request pending 0 : No request D[2] DRQAOUT Audio output DMA transfer request 1 : Request pending 0 : No request D[1] Reserved Write 0 when writing. 0 is returned after a read. D[0] DRQFOUT FIR transmission DMA transfer request 1 : Request pending 0 : No request This register is used to indicate whether or not there are any DMA transfer requests. |
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