VR4102 datasheet(382/701 Pages) NEC

382 / 701 page

CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT)

382

19.1.1 Block Diagrams

Figure 19-1. PIU Peripheral Block Diagram

TPY1

TPY0

TPX1

TPX0

AUDIOIN

ADIN2

ADIN1

ADIN0

ADC

AIU

PIU

VR4102

I/O

buffer

Battery, etc.

Touch panel

I/O

buffer

• Touch panel

A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have

high resistance when there is no pen contact and low resistance when there is pen contact. The resistance

between the two edges of the resistance layers is about 1 k

:. When a voltage is applied to both edges of the

Y-axis resistance layer, the voltage (VY1 and VY2 in the figure below) is measures at the X-axis resistance

layer’s pins to determine the Y coordinate. Similarly, when a voltage is applied to both edges of the X-axis

resistance layer, the voltage (VX1 and VX2 in the figure below) is measures at the Y-axis resistance layer’s

pins to determine the X coordinate. For greater precision, voltage applied to individual resistance-layer pins

can be measured to obtain X and Y coordinate data based on four voltage measurements. The obtained

coordinate data are stored to PIUPBnmREG register (n = 0, 1, m = 0 to 3).

Figure 19-2. Equivalent Circuit of Coordinate Detection

(a) Y-coordinate detection

TPY1: 3V

TPY1: 0V

TPY0: 0V

TPY0: 3V

TPX0

TPY0

(b) X-coordinate detection

TPY0

TPX0: 3V

TPX1: 0V

TPX0: 0V

TPX1: 3V

VY2

VY1

VX1

VX2

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