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VR4102 Datasheet(PDF) 639 Page - NEC |
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VR4102 Datasheet(HTML) 639 Page - NEC |
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639 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 639 SRA Shift Right Arithmetic SRA 0 0 0 0 0 0 SPECIAL 0 0 0 0 0 0 rt rd sa SRA 0 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits. The result is placed in register rd. In 64-bit mode, the operand must be a valid sign-extended, 32-bit value. Operation: 32 T: GPR [rd] <- (GPR [rt]31) sa || GPR [rt]31...sa 64 T: s <- 0 || sa temp <- (GPR [rt]31) s || GPR [rt] 31...s GPR [rd] <- (temp31) 32 || temp Exceptions: None |
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