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VR4102 Datasheet(PDF) 643 Page - NEC |
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VR4102 Datasheet(HTML) 643 Page - NEC |
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643 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 643 STANDBY Standby STANDBY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COP0 0 1 0 0 0 0 STANDBY 1 0 0 0 0 1 31 26 25 6 5 0 619 6 CO 1 1 24 Format: STANDBY Description: STANDBY instruction starts mode transition from Fullspeed mode to Standby mode. When the STANDBY instruction finishes the WB stage, the VR4102 wait by the SysAD bus is idle state, after then the internal clocks will shut down, thus freezing the pipeline. The PLL, Timer/Interrupt clocks and the internal bus clocks (TClock and MasterOut) will continue to run. Once the VR4102 is in Standby mode, any interrupt, including the internally generated timer interrupt, NMI, Soft Reset, and Cold Reset will cause the VR4102 to exit Standby mode and to enter Fullspeed mode. Operation: 32, 64 T: T+1: Standby operation () Exceptions: Coprocessor unusable exception Remark Refer to Chapter 15 for details about the operation of the peripheral units at mode transition. |
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