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VR4102 Datasheet(PDF) 645 Page - NEC |
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VR4102 Datasheet(HTML) 645 Page - NEC |
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645 / 701 page  CHAPTER 27 CPU INSTRUCTION SET DETAILS 645 SUBU Subtract Unsigned SUBU rs SPECIAL 0 0 0 0 0 0 rt rd 0 0 0 0 0 0 SUBU 1 0 0 0 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5555 6 Format: SUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result. The result is placed into general register rd. In 64-bit mode, the operands must be valid sign-extended, 32-bit values. The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow. No integer overflow exception occurs under any circumstances. Operation: 32 T: GPR [rd] <- GPR [rs] - GPR [rt] 64 T: temp <- GPR [rs] - GPR [rt] GPR [rd] <- (temp31) 32 || temp 31...0 Exceptions: None |
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