VR4102 datasheet(649/701 Pages) NEC

649 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

649

SWL

Store Word Left

SWL

(Continued)

Operation:

vAddr <- ((offset15)

16 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

)

if BigEndianMem = 0 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

if (vAddr2 xor BigEndianCPU) = 0 then

data <- 0

|| 0

24 – 8 * byte

|| GPR [rt]31...24 – 8 * byte

else

data <- 0

24 – 8 * byte || GPR [rt]

31...24 – 8 * byte || 0

endif

StoreMemory (uncached, byte, data, pAddr, vAddr, DATA)

vAddr <- ((offset15)

48 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

)

if BigEndianMem = 0 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

if (vAddr2 xor BigEndianCPU) = 0 then

data <- 0

32 || 024 – 8 * byte || GPR [rt]31...24 – 8 * byte

else

data <- 0

24 – 8 * byte

|| GPR [rt]31...24 – 8 * byte || 0

endif

StoreMemory (uncached, byte, data, pAddr, vAddr, DATA)

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