VR4102 datasheet(652/701 Pages) NEC

652 / 701 page

CHAPTER 27 CPU INSTRUCTION SET DETAILS

652

SWR

Store Word Right

SWR

(Continued)

Operation:

vAddr <- ((offset15)

16 || offset15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

if BigEndianMem = 1 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

if (vAddr2 xor BigEndianCPU) = 0 then

data <- 0

32 || GPR [rt]31 – 8 * byte...0 || 08 * byte

else

data <- GPR [rt]31 – 8 * byte || 0

8 * byte || 032

endif

StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)

vAddr <- ((offset15)

48 || offset

15...0) + GPR [base]

(pAddr, uncached) <- AddressTranslation (vAddr, DATA)

pAddr <- pAddrPSIZE - 1...3 || (pAddr2...0 xor ReverseEndian

if BigEndianMem = 1 then

pAddr <- pAddrPSIZE - 1...2 || 0

endif

byte <- vAddr1...0 xor BigEndianCPU

if (vAddr2 xor BigEndianCPU) = 0 then

data <- 0

32 || GPR [rt]

31 – 8 * byte...0 || 0

8 * byte

else

data <- GPR [rt]31 – 8 * byte || 0

8 * byte || 032

endif

StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)

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